直角坐标在软件开发中的应用研究

为简化不同软件开发技术处理界面中组件关系的算法,增强使用数学模型解决软件开发中算法设计的能力,全面分析和总结直角坐标系在界面设计中的应用十分必要。通过对不同开发技术处理界面设计的分析,界面中组件位置关系实质上都可以转化为坐标关系的计算。本文列举了直角坐标系在Python编程、Android编程、Java编程和Unity编程中的应用,以期给相应的算法设计提供借鉴思路。     

基于残差决策的自动飞行控制系统远程实时故障诊断

针对自动飞行控制系统结构复杂、关联部件众多,发生故障时诊断时间长,从而影响飞机运行效率的问题,提出一种基于飞机通信寻址报告系统(ACARS)的远程实时故障诊断方案。首先,分析自动飞行控制系统的故障特点,设计搭建检测滤波器;然后,利用ACARS数据链实时发送的自动飞行控制系统的关键信息进行相关部件的残差计算,并根据残差决策算法进行故障诊断及定位;最后,针对不同故障部件残差间的差异大、决策门限无法统一的缺点,提出基于二次差值的残差决策改进算法,减缓了检测对象的整体变化趋势,降低了随机噪声和干扰的影响,避免了将瞬态故障诊断为系统故障的情况。实验仿真结果表明,基于二次差值的改进残差决策算法避免了多决策门限的复杂性,在采样时间为0.1 s的情况下,故障检测所需时间大约为2 s,故障检测时间大幅降低,有效故障检测率大于90%。     

铜浮选专家控制系统设计与应用

针对国内某选矿厂铜浮选工艺泡沫速率不稳定,精矿品位波动大,回收率不理想等特点,设计了一套浮选专家控制系统,该系统结合泡沫影像分析技术,在线品位分析技术,PID控制与模糊逻辑控制技术。系统架构简明合理,逻辑层次清晰有效,投入运行一段时间后,在不同原矿品位前提下,都能实现稳定泡沫速率,减少精矿品位波动,提高回收率等指标优化,同时药剂添加量也有明显减少。这表明该系统运行效果良好,值得应用推广。     

Weighted Superposition Attraction (WSA): A swarm intelligence algorithm for optimization problems – Part 2: Constrained optimization

This paper is the second one of the two papers entitled “Weighted Superposition Attraction (WSA) Algorithm”, which is about the performance evaluation of the WSA algorithm in solving the constrained global optimization problems. For this purpose, the well-known mechanical design optimization problems, design of a tension/compression coil spring, design of a pressure vessel, design of a welded beam and design of a speed reducer, are selected as test problems. Since all these problems were formulated as constrained global optimization problems, WSA algorithm requires a constraint handling method for tackling them. For this purpose we have selected 6 formerly developed constraint handling methods for adapting into WSA algorithm and analyze the effect of the used constraint handling method on the performance of the WSA algorithm. In other words, we have the aim of producing concluding remarks over the performance and robustness of the WSA algorithm through a set of computational study in solving the constrained global optimization problems. Computational study indicates the robustness and the effectiveness of the WSA in terms of obtained results, reached level of convergence and the capability of coping with the problems of premature convergence, trapping in a local optima and stagnation.     

一种北斗联合低轨星座的导航增强方法研究

单纯依靠北斗导航系统提供定位导航授时服务,存在卫星信号落地功率低、易受遮蔽和阻断的不足。针对此问题,研究了一种北斗联合低轨星座实现导航增强的系统架构;提出了一种新的适应严重遮蔽或干扰条件下,基于到达时间(TOA)和到达频率(FOA)联合观测的定位解算算法;对高中低轨混合星座条件下的覆盖特性和精度衰减因子进行了仿真分析。分析结果表明,用户可见星数平均增加了64.2%,位置精度衰减因子(PDOP)平均改善了28.7%。研究结果可为下一代北斗的论证设计与研制建设提供参考借鉴。     

基于多项式变换的参数估计方法

本文给出一种采用DPT估计SNCK信号时宽—带宽积的方法,并通过仿真该估计方法的性能与其它估计方法进行比较.首先给出SNCK信号参数估计的一般过程.为了便于计算和理论推导,根据估计出的中心频率将接收到的SNCK信号搬移到零频,从而进一步估计其它参数,如采用DPT估计SNCK信号时宽带宽积.本文将重点研究采用DPT算法估计SNCK信号值的方法.     

快递分拣机器人控制系统的设计

为提高快递分拣效率,设计了一种基于OpenMV机器视觉模块的快递分拣机器人控制系统。在这一控制系统中,通过机器视觉技术实现快递件的轮廓识别、定位、扫码及分类,将STM32单片机作为运动控制核心,外接传感器感知机器人的状态,基于串口与机器视觉模块双向通信,实现对放置在地面的快递件进行自动分拣。通过制作样机验证了设计的合理性与可行性。     

Compiler compatible 5.66 Mb/mm2 8T 1R1W register file in 14 nm FinFET technology

1-read/1-write (1R1W) register file (RF) is a popular memory configuration in modern feature rich SoCs requiring significant amount of embedded memory. A memory compiler is constructed using the 8T RF bitcell spanning a range of instances from 32 b to 72 Kb. An 8T low-leakage bitcell of 0.106 μm² is used in a 14 nm FinFET technology with a 70 nm contacted gate pitch for high-density (HD) two-port (TP) RF memory compiler which achieves 5.66 Mb/mm² array density for a 72 Kb array which is the highest reported density in 14 nm FinFET technology. The density improvement is achieved by using techniques such as leaf-cell optimization (eliminating transistors), better architectural planning, top level connectivity through leaf-cell abutment and minimizing the number of unique leaf-cells. These techniques are fully compatible with memory compiler usage over the required span. Leakage power is minimized by using power-switches without degrading the density mentioned above. Self-induced supply voltage collapse technique is applied for write and a four stack static keeper is used for read Vmin improvement. Fabricated test chips using 14 nm process have demonstrated 2.33 GHz performance at 1.1 V/25 °C operation. Overall V_min of 550 mV is achieved with this design at 25 °C. The inbuilt power-switch improves leakage power by 12x in simulation. Approximately 8% die area of a leading 14 nm SoC in commercialization is occupied by these compiled RF instances.     

SIS在赛科项目中的应用

目前，国内很多项目对安全仪表系统要求不是很严格，但随着人们对装置安全及人员保护更加深刻的认识，这类安全仪表系统会得到越来越多的重视和应用。简单介绍了SIS在赛科装置中的应用，SIS各个生命周期以及具体实施的方法，列出了安全度等级，要求故障概率等数据的计算方法。